Device and circuit modeling of nano-cmos
The demand for more and ever smaller portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects,...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Book Section |
| Published: |
Penerbit UTM
2012
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/47760/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | The demand for more and ever smaller portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturisation. To enable even smaller electronics, various nano-devices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels. |
|---|