Design for testability I: from full scan to partial scan

• Main Author: Chia, Yee Ooi
• Format: Book Section
• Language: English
• Published: Penerbit UTM 2008
• Subjects: T Technology (General)
• Online Access: http://eprints.utm.my/id/eprint/31036/1/ChiaYeeOoi2008_DesignforTestabilityIFromFullScantoPartial.pdf; http://eprints.utm.my/id/eprint/31036/

It is important to check whether the manufactured circuit has physical defects or not. Else, the defective part may adversely affect the circuit's functioning. The checking process is called testing or manufacturing test. In other words, manufacturing test is an important step in VLSI realization process. Figure 6.1 shows the process. As can be seen in Figure 6.1, there is a stage called test development where it basically consists of three activities; test generation, fault simulation and design for testability implementation. Test generation is a method of generating an input sequence that can distinguish between good chip and defective chip when the input sequence (test sequence) is applied to the chip using a tester. Fault simulation is a step of simulating circuits in the presence of faults. This step is used to evaluate the quality of a set of test sequence by indicating the fault coverage of the test sequence applied to a circuit.