USB soft core with altera Nios processor

• Main Author: Cheah, Chee Teong
• Format: Thesis
• Language: English
• Published: 2007
• Subjects: TK Electrical engineering. Electronics Nuclear engineering; QA75 Electronic computers. Computer science
• Online Access: http://eprints.utm.my/id/eprint/263/1/CheahCheeTeongMFKE2007.pdf; http://eprints.utm.my/id/eprint/263/

This objectives of this project learning the process of implementing an System-on-Chip (SoC) using the Altera development board. The chosen board is the Excalibur board which consists of the APEX 20KE200 FPGA. Besides this, Quartus II software is needed as the platform for the development of this project. USB was used as example soft core component to be added to the SoC with the IP obtained from the Opencores web site. As the Nios the system uses the Avalon bus system, while the USB IP core is built for Wishbone bus system, a bridge which allows the both bus systems to communicate was required. This project succeeded in proving the functionality of the bridge. The USB core can either be programmed as Host or Slave. For the USB to communicate to the outside world, physical (PHY) layer circuit was required. The PHY chip used was the Fairchild USB1T11A. To build the PHY printed circuit board (PCB), the Santa Cruz connector located on the Altera development board was used. The PHY circuitry was built on a PCB which was then plugged into the Santa Cruz connector. The final task for the project was testing the USB driver.