The Implementation of a pipelined floating-point cordic coprocessor on Nios Ii soft processor
This paper discusses the implementation of a pipelined floating-point Coordinate Rotation Digital Computer (CORDIC) coprocessor using Field Programmable Gate Array (FPGA) to accelerate the computation speed in solving elementary functions on NIOS II soft processor. Examples of the elementary functio...
Saved in:
Main Authors: | , , , |
---|---|
Format: | Article |
Published: |
IJEEDC
2015
|
Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/60468/ http://ijeedc.iraj.in/volume.php?volume_id=124 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|