Optimization of 14nm horizontal double gate for optimum threshold voltage Using L9 Taguchi method

• Main Authors: Abdul Hamid, Afifah Maheran, N.H.N.M. Nizam, Salehuddin, Fauziyah, Kaharudin, Khairil Ezwan, Zainul Abidin, Noor Faizah
• Format: Article
• Language: English
• Published: UniMAP Press 2022
• Online Access: http://eprints.utem.edu.my/id/eprint/26767/2/SPECIAL%20ISSUE%20IJNEAM_VOL_15_SI_DECEMBER_2022_255-265.PDF; http://eprints.utem.edu.my/id/eprint/26767/; https://ijneam.unimap.edu.my/images/PDF/SPECIAL%20ISSUE%20BOND%202022/Vol_15_SI_December_2022_255-265.pdf

Silvaco ATHENA TCAD tools are used to model and simulate the electrical properties and characterization of the suggested layout of a 14 nm gate length (Lg) Double Gate Bilayer Graphene Field Effect Transistor (FET). Hafnium Dioxide (HfO2) serves as the high-k material in the negative channel metal oxide semiconductor (NMOS) device, while Tungsten Silicide (WSix) serves as the metal gate. The investigated process parameters are threshold voltage (VTH) adjustment implant dose, threshold voltage (VTH) adjustment tilt angle, source/drain (S/D) implant tilt angle, and source/drain (S/D) implant dose, while the noise factors are threshold voltage (VTH) adjustment implant energy and source-drain (S/D) implant energy. The device was optimized using the Taguchi approach, which incorporates L9 orthogonal arrays and analysis of variance (ANOVA). The most important elements impacting the VTH are the S/D implantation dose. The value of the VTH when compared to the original findings before the optimization is 0.204V, which is 7.059% lower than the desired value. The findings of the optimization procedure show excellent efficiency of the device with a VTH of 0.191, which is 0.007% closer to the 2013 target set by the International Technology Roadmap Semiconductor (ITRS).