Geometric And Process Design Of Ultra-Thin Junctionless Double Gate Vertical MOSFETs

• Main Authors: Salehuddin, Fauziyah, Kaharudin, Khairil Ezwan, Mohd Zain, Anis Suhaila, Roslan, Ameer Farhan
• Format: Article
• Language: English
• Published: Institute of Advanced Engineering and Science 2019
• Online Access: http://eprints.utem.edu.my/id/eprint/24222/2/KEKAHARUDIN-IJECE-AUGUST2019.PDF; http://eprints.utem.edu.my/id/eprint/24222/; http://ijece.iaescore.com/index.php/IJECE/article/view/12742/13114

The junctionless MOSFET architectures appear to be attractive in realizing the Moore's law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.