Investigation and statistical simulation of variation aware 14nm SRAM cache memory architecture

• Main Author: Pour, Somayeh Rahimi
• Format: Thesis
• Language: English
• Published: 2011
• Online Access: http://psasir.upm.edu.my/id/eprint/41628/1/FK%202011%20121R.pdf; http://psasir.upm.edu.my/id/eprint/41628/

Aggressive technology scaling to 14 nm technology node increases variability in transistors performance and introduces serious reliability challenges to the design of microprocessors. This creates several challenges in building reliable systems from transistors with unpredictability of delay. Scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM cache. Since a large fraction of chip area is devoted to on-chip caches, it is important to protect these SRAM structures against failures. The intrinsic parameter fluctuation within a cache can lead to variability in the behavior of the different transistors and is the most noticeable type of variation that resulting in a violation of delay requirements and uncertainty. These variations have an increasing impact on cache performance and yield because the transistors used in cache are among the minimal size for each particular technology generation. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuations on cache important parameters. The cache performance is evaluated in terms of cache hit ratio and cache miss penalty. This methodology captures the intrinsic parameter fluctuations information from circuit level and provides essential link between circuit-level simulation and systemlevel simulation. In order to study the impact of intrinsic parameter fluctuations percentage of accesses that result in cache miss (cache miss ratio), in the presence of different source of intrinsic parameter fluctuations is investigated. Cache misses happen when the required data for reading or writing is not in the cache or there is an access time failure. However, as the electrical parameters of the transistors are prone to intrinsic fluctuations, the access time varies from memory cell to memory cell. When the access time of a cell is longer than the maximum tolerable limit (TMAX), an access time failure is said to have occurred, and that cell considered as a faulty cell. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a 25 nm, 20 nm and 14 nm technology node is performed. From systemspoint of view, the intrinsic parameter fluctuations must be captured in behavioral level which can be used in system simulators like Icarus Verilog HDL. The impact of intrinsic parameter fluctuations on cache miss penalty time causes significantly failures in cache performance. Therefore, it is important to consider alternative cache architectures that are more tolerable to intrinsic parameter fluctuations. A new variation aware cache architecture is proposed to reduce the impact of the intrinsic parameter fluctuations in cache in nanoscale regime. This technique enables TLB to access just the non faulty words with negligible area overhead. Experimental results on a 32K fully associative L1 cache show that the proposed architecture can achieve 85% reduction in cache miss penalty.