An Efficient Architecture of 8-Bit CMOS Analog-To-Digital Converter
An 8-bit CMOS analog-to-digital converter (ADC) has been designed by using a more efficient architecture, which is known as the simplified multistep flash architecture. This architecture can ultimately reduce the number of comparators needed in an ADC. For the same resolutions, the full-flash archit...
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Main Author: | Tan, Philip Beow Yew |
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Format: | Thesis |
Language: | English English |
Published: |
2000
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Subjects: | |
Online Access: | http://psasir.upm.edu.my/id/eprint/10664/1/FK_2000_47.pdf http://psasir.upm.edu.my/id/eprint/10664/ |
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