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Solder bump strength and failure mode of low-k flip chip device

In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is...

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Main Authors: Endut, Z., Ahmad, I., Swee, G.L.H., Sukemi, N.M.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5305
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spelling my.uniten.dspace-53052017-11-15T02:57:25Z Solder bump strength and failure mode of low-k flip chip device Endut, Z. Ahmad, I. Swee, G.L.H. Sukemi, N.M. In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging. ©2006 IEEE. 2017-11-15T02:57:25Z 2017-11-15T02:57:25Z 2006 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5305
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging. ©2006 IEEE.
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author Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
spellingShingle Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
Solder bump strength and failure mode of low-k flip chip device
author_facet Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
author_sort Endut, Z.
title Solder bump strength and failure mode of low-k flip chip device
title_short Solder bump strength and failure mode of low-k flip chip device
title_full Solder bump strength and failure mode of low-k flip chip device
title_fullStr Solder bump strength and failure mode of low-k flip chip device
title_full_unstemmed Solder bump strength and failure mode of low-k flip chip device
title_sort solder bump strength and failure mode of low-k flip chip device
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5305
_version_ 1644493652149403648
score 13.211869

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