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Impact of low-k devices on failure mode of flip chip tensile pull test

In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is...

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Main Authors: Endut, Z., Ahmad, I., Swee, G.L.H., Sukemi, N.M.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5303
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spelling my.uniten.dspace-53032017-11-15T02:57:24Z Impact of low-k devices on failure mode of flip chip tensile pull test Endut, Z. Ahmad, I. Swee, G.L.H. Sukemi, N.M. In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging. ©2006 IEEE. 2017-11-15T02:57:24Z 2017-11-15T02:57:24Z 2006 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5303
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging. ©2006 IEEE.
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author Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
spellingShingle Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
Impact of low-k devices on failure mode of flip chip tensile pull test
author_facet Endut, Z.
Ahmad, I.
Swee, G.L.H.
Sukemi, N.M.
author_sort Endut, Z.
title Impact of low-k devices on failure mode of flip chip tensile pull test
title_short Impact of low-k devices on failure mode of flip chip tensile pull test
title_full Impact of low-k devices on failure mode of flip chip tensile pull test
title_fullStr Impact of low-k devices on failure mode of flip chip tensile pull test
title_full_unstemmed Impact of low-k devices on failure mode of flip chip tensile pull test
title_sort impact of low-k devices on failure mode of flip chip tensile pull test
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5303
_version_ 1644493651569541120
score 13.222552

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