Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

• 主要な著者: Elgomati, H.A., Majlis, B.Y., Ahmad, I., Salehuddin, F., Hamid, F.A., Zaharim, A., Apte, P.R.
• フォーマット: 論文
• 出版事項: 2017
• オンライン･アクセス: http://dspace.uniten.edu.my:80/jspui/handle/123456789/5239

In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determi...