Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device
In this study, Taguchi method was used to optimize the influence of process parameter variations on threshold voltage (VTH) in 45 nm n-channel metal oxide semiconductor (NMOS) device. The orthogonal array, the signal-to-noise ratio, and analysis of variance were employed to study the performance cha...
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my.uniten.dspace-52382018-03-02T03:28:51Z Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device Salehuddin, F. Ahmad, I. Hamid, F.A. Zaharim, A. Hashim, U. Apte, P.R. In this study, Taguchi method was used to optimize the influence of process parameter variations on threshold voltage (VTH) in 45 nm n-channel metal oxide semiconductor (NMOS) device. The orthogonal array, the signal-to-noise ratio, and analysis of variance were employed to study the performance characteristics of a device. In this paper, eleven process parameters (control factors) were varied for 2 levels to perform 12 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using technology computer-aided design (TCAD) simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, compensation implantation energy was identified as one of the process parameters that have the strongest effect on the response characteristics. While the halo implantation dosage was identified as an adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.176 V. © 2011 Academic Journals. 2017-11-15T02:56:55Z 2017-11-15T02:56:55Z 2011 Article http://dspace.uniten.edu.my:80/jspui/handle/123456789/5238 10.5897/IJPS11.401 |
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In this study, Taguchi method was used to optimize the influence of process parameter variations on threshold voltage (VTH) in 45 nm n-channel metal oxide semiconductor (NMOS) device. The orthogonal array, the signal-to-noise ratio, and analysis of variance were employed to study the performance characteristics of a device. In this paper, eleven process parameters (control factors) were varied for 2 levels to perform 12 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using technology computer-aided design (TCAD) simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, compensation implantation energy was identified as one of the process parameters that have the strongest effect on the response characteristics. While the halo implantation dosage was identified as an adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.176 V. © 2011 Academic Journals. |
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Article |
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Salehuddin, F. Ahmad, I. Hamid, F.A. Zaharim, A. Hashim, U. Apte, P.R. |
spellingShingle |
Salehuddin, F. Ahmad, I. Hamid, F.A. Zaharim, A. Hashim, U. Apte, P.R. Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
author_facet |
Salehuddin, F. Ahmad, I. Hamid, F.A. Zaharim, A. Hashim, U. Apte, P.R. |
author_sort |
Salehuddin, F. |
title |
Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
title_short |
Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
title_full |
Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
title_fullStr |
Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
title_full_unstemmed |
Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device |
title_sort |
optimization of input process parameters variation on threshold voltage in 45 nm nmos device |
publishDate |
2017 |
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http://dspace.uniten.edu.my:80/jspui/handle/123456789/5238 |
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13.18916 |