Modelling of process parameters for 32nm PMOS transistor using Taguchi method
As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transis...
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| 主要な著者: | , , , , |
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2017
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| オンライン･アクセス: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5226 |
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