Optimization of process parameter variations on threshold voltage in Ultrathin Pillar Vertical Double Gate MOSFET Device

• Main Authors: Kaharudin, K.E., Hamidon, A.H., Salehuddin, F., Ifwat Abd Aziz, M.N., Ahmad, I.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5191

In the fabrication of MOSFET devices, the process parameters play a very important role in deciding the MOSFET device's characteristics. The process parameter variations may contribute a significant impact on the dopant profiles that directly affect the device characteristics. These variations cause significant unpredictability in the power and performance characteristics of the device that may cause the degradation of the device performance. Therefore, a special technique involving design and analytical experiments is required to identify the process parameters that contribute the most of these variations In this current study, the L27 orthogonal array of Taguchi method was utilized to optimize the variability of process parameters on threshold voltage (VTH) in Ultrathin Pillar Vertical Double Gate MOSFET Device. This work was initially performed by using Silvaco technology computer-aided design (TCAD) simulator consisted of a process simulator (ATHENA) and a device simulator (ATLAS). These two simulators were combined with the L27 orthogonal array of Taguchi method in order to obtain the robust design recipe. The results revealed that the halo implant tilt was the most dominant process parameter that had the strongest effect on threshold voltage (VTH). Meanwhile, halo implant dose was selected as an adjustment factor in order to obtain the desired threshold voltage (VTH) value. The most optimum VTH value was observed to be 0.443 V and it is only 0.89% lower than the target or nominal value (0.447 V). This value is still within the predicted range of ITRS 2013 for low power (LP) multi-gate (MG) technology requirement in the year 2020. © 2006-2016 Asian Research Publishing Network (ARPN).