Design of a reconfigurable computing platform

• Main Authors: Papu J.J., See O.H.
• Other Authors: 35119451300
• Format: Conference paper
• Published: 2023
• Subjects: Computer hardware; Computer science; Design; Field programmable gate arrays (FPGA); Industrial applications; Integrated circuits; Intelligent systems; Lithography; Luminous paint; Bit stream; Co-processors; E-field; Electronic system level design; General purpose processors; Hardware and software; Hardware design; High-performance computing applications; Implementation process; Nallatech; Programmable gate array; Reconfigurable computing; Source codes; Computer hardware description languages

This paper describes a design of a reconfigurable computing platform (RCP) based on the Intel Xeon general purpose processor and the Nallatech BenNUEY-PCI-4E field programmable gate array (FPGA) motherboard. The RCP is built to allow users with little or no knowledge of hardware design to program high performance computing applications that utilizes FPGA as the coprocessor. The RCP utilizes Impulse CoDeveloper which is an electronic system level (ESL) design tool that compiles sequential applications/algorithms in C to synthesizable HDL. A customized platform support package (PSP) was developed within the Impulse CoDeveloper environment to enable the Impulse tools to automatically generate the HDL files and C source codes with supported hardware and software interfaces that is targeted for the RCP. The PSP also automates the synthesis and implementation process integration to generate the bitstream file from the Xilinx ISE foundation tool. Finally, the RCP is made accessible within a LAN with the FUSE TCP/IP Server tool. � 2009 IEEE.