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Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system

The optimisation of combined built-in self-test (BIST) and automatic test equipment (ATE) is desirable for complex fabricated chip testing to meet the high fault coverage while preserving acceptable costs. The fault coverage of BIST and ATE plays a significant role, because it can affect the area ov...

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Bibliographic Details
Main Authors: Islam S.Z., Ali M.A.M.
Other Authors: 55432804400
Format: Article
Published: Institution of Engineers (Australia) 2023
Subjects:
Automatic testing
Equipment testing
Integrated circuit testing
Integration testing
Mixed signal integrated circuits
Reconfigurable hardware
Semiconductor device manufacture
System-on-chip
Timing circuits
VLSI circuits
Automatic test equipment
Circuit testing
Fabricated chips
Fault coverages
Hybrid techniques
Reconfigurable
Test pattern generations
Very-large-scale integration circuits
Built-in self test
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spelling my.uniten.dspace-306562023-12-29T15:50:54Z Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system Islam S.Z. Ali M.A.M. 55432804400 6507416666 Automatic testing Equipment testing Integrated circuit testing Integration testing Mixed signal integrated circuits Reconfigurable hardware Semiconductor device manufacture System-on-chip Timing circuits VLSI circuits Automatic test equipment Circuit testing Fabricated chips Fault coverages Hybrid techniques Reconfigurable Test pattern generations Very-large-scale integration circuits Built-in self test The optimisation of combined built-in self-test (BIST) and automatic test equipment (ATE) is desirable for complex fabricated chip testing to meet the high fault coverage while preserving acceptable costs. The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. In this paper, a test circuit system (TCS) employing the hybrid technique (combined BIST/ATE) of test pattern generation is presented. The very large scale integration (VLSI) circuit testing features of the hybrid technique overcome the requirements for expensive ATE, as well as extra silicon area in BIST applications. The extendable input/output bus and IDDQ features for the TCS are also shown to enhance the testing capacity corresponding to recent VLSI circuit and system-on-chip requirements. � Institution of Engineers Australia, 2010. Final 2023-12-29T07:50:54Z 2023-12-29T07:50:54Z 2010 Article 10.1080/1448837X.2010.11464259 2-s2.0-78651369008 https://www.scopus.com/inward/record.uri?eid=2-s2.0-78651369008&doi=10.1080%2f1448837X.2010.11464259&partnerID=40&md5=652b782701d3e1393dcc3e2c8e883394 https://irepository.uniten.edu.my/handle/123456789/30656 7 1 73 82 Institution of Engineers (Australia) Scopus
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
topic Automatic testing
Equipment testing
Integrated circuit testing
Integration testing
Mixed signal integrated circuits
Reconfigurable hardware
Semiconductor device manufacture
System-on-chip
Timing circuits
VLSI circuits
Automatic test equipment
Circuit testing
Fabricated chips
Fault coverages
Hybrid techniques
Reconfigurable
Test pattern generations
Very-large-scale integration circuits
Built-in self test
spellingShingle Automatic testing
Equipment testing
Integrated circuit testing
Integration testing
Mixed signal integrated circuits
Reconfigurable hardware
Semiconductor device manufacture
System-on-chip
Timing circuits
VLSI circuits
Automatic test equipment
Circuit testing
Fabricated chips
Fault coverages
Hybrid techniques
Reconfigurable
Test pattern generations
Very-large-scale integration circuits
Built-in self test
Islam S.Z.
Ali M.A.M.
Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
description The optimisation of combined built-in self-test (BIST) and automatic test equipment (ATE) is desirable for complex fabricated chip testing to meet the high fault coverage while preserving acceptable costs. The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. In this paper, a test circuit system (TCS) employing the hybrid technique (combined BIST/ATE) of test pattern generation is presented. The very large scale integration (VLSI) circuit testing features of the hybrid technique overcome the requirements for expensive ATE, as well as extra silicon area in BIST applications. The extendable input/output bus and IDDQ features for the TCS are also shown to enhance the testing capacity corresponding to recent VLSI circuit and system-on-chip requirements. � Institution of Engineers Australia, 2010.
author2 55432804400
author_facet 55432804400
Islam S.Z.
Ali M.A.M.
format Article
author Islam S.Z.
Ali M.A.M.
author_sort Islam S.Z.
title Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
title_short Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
title_full Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
title_fullStr Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
title_full_unstemmed Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system
title_sort implementation of low-cost reconfigurable external mixed-signal vlsi circuit testing system
publisher Institution of Engineers (Australia)
publishDate 2023
_version_ 1806424110559920128
score 13.214268

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