Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage

• Main Authors: Elgomati H.A., Majlis B.Y., Salehuddin F., Ahmad I., Zaharim A., Hamid F.A.
• Other Authors: 36536722700
• Format: Conference paper
• Published: 2023
• Subjects: 35nm NMOS; halo implantation; taguchi; Arsenic; Experiments; Grain boundaries; Ion implantation; Ions; Leakage currents; MOS devices; Phosphorus; Polycrystalline materials; Polysilicon; Silicon wafers; Threshold voltage; Active area; CMOS transistors; Doping concentration; Electrical characteristic; Electrical characterization; Electrical limitations; Fabrication process; Halo ion implantation; High-speed chips; Key technologies; NMOS devices; NMOS transistors; Poly-crystalline silicon; Scaling down; Short-channel effect; Silvaco; Taguchi analysis; Transistors

CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical...