Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method
This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold v...
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my.uniten.dspace-238152023-05-29T14:52:04Z Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method Bte Atanb N. Majlis B.Y. Ahmad I. Chong K.H. 57201393384 6603071546 12792216600 36994481200 This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 � 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012. � 2018 Institute of Advanced Engineering and Science. All rights reserved. Final 2023-05-29T06:52:04Z 2023-05-29T06:52:04Z 2018 Article 10.11591/ijeecs.v10.i3.pp934-942 2-s2.0-85044584855 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85044584855&doi=10.11591%2fijeecs.v10.i3.pp934-942&partnerID=40&md5=921b037421bb2ec804b784eb09d52e24 https://irepository.uniten.edu.my/handle/123456789/23815 10 3 934 942 All Open Access, Green Institute of Advanced Engineering and Science Scopus |
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This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 � 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012. � 2018 Institute of Advanced Engineering and Science. All rights reserved. |
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57201393384 |
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57201393384 Bte Atanb N. Majlis B.Y. Ahmad I. Chong K.H. |
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Bte Atanb N. Majlis B.Y. Ahmad I. Chong K.H. |
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Bte Atanb N. Majlis B.Y. Ahmad I. Chong K.H. Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
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Bte Atanb N. |
title |
Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
title_short |
Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
title_full |
Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
title_fullStr |
Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
title_full_unstemmed |
Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method |
title_sort |
analysis the effect of control factors optimization on the threshold voltage of 18 nm pmos using l27 taguchi method |
publisher |
Institute of Advanced Engineering and Science |
publishDate |
2023 |
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1806425674794139648 |
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13.18916 |