High degree of testability using full scan chain and ATPG-An industrial perspective
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Asian Network for Scientific Information
2010
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my.unimap-91702010-08-26T07:49:39Z High degree of testability using full scan chain and ATPG-An industrial perspective Mamun, Ibne Reaz Lee, W. F. Hamid, N. H. Lo, H. H. Ali Yeon, Mohd Shakaff, Prof. Dr. Automatic test pattern generation Design for test DFT design methodology Guideline IC chip packaging Integrated circuit Scan chain Sharing pin for testing VLSI Link to publisher's homepage at www.ansinet.com/ This study describes an efficient design methodology from an industrial perspective on utilizing Register Transfer Level (RTL) coding style, full scan chain implementation and Automatic Test Pattern Generation (ATPG) to achieve a high percentage of testability in the final Integrated Circuit (IC). The design methodology involves using an ASIC design flow with scan insertion and scan stitching performed after synthesis with scan flops set as don’t_use during synthesis process. Based on this method of ASIC design flow with the RTL coding style and guideline, an in-house 64 bit processor core that executes 3 instructions per cycle, is implemented with 0.35 micron process technology with a single scan chain of 4600 flip-flops, achieving an ATPG pattern for stuck-at at 100% test coverage and 99.81% fault coverage. Thus, creating high testability coverage with the ATPG pattern can be achieved by having a fully synchronous design using the proposed RTL coding style and full scan chain implementation. This study also describes the work around methods used when dealing with cost reduction involving reduction of test pin on the IC chip package. 2010-08-26T07:47:16Z 2010-08-26T07:47:16Z 2009 Article Journal of Applied Sciences, vol. 9(14), 2009, pages 2613-2618 1812-5654 http://www.scialert.net/pdfs/jas/2009/2613-2618.pdf http://hdl.handle.net/123456789/9170 en Asian Network for Scientific Information |
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Universiti Malaysia Perlis |
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Asia |
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Malaysia |
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Universiti Malaysia Perlis |
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http://dspace.unimap.edu.my/ |
| language |
English |
| topic |
Automatic test pattern generation Design for test DFT design methodology Guideline IC chip packaging Integrated circuit Scan chain Sharing pin for testing VLSI |
| spellingShingle |
Automatic test pattern generation Design for test DFT design methodology Guideline IC chip packaging Integrated circuit Scan chain Sharing pin for testing VLSI Mamun, Ibne Reaz Lee, W. F. Hamid, N. H. Lo, H. H. Ali Yeon, Mohd Shakaff, Prof. Dr. High degree of testability using full scan chain and ATPG-An industrial perspective |
| description |
Link to publisher's homepage at www.ansinet.com/ |
| format |
Article |
| author |
Mamun, Ibne Reaz Lee, W. F. Hamid, N. H. Lo, H. H. Ali Yeon, Mohd Shakaff, Prof. Dr. |
| author_facet |
Mamun, Ibne Reaz Lee, W. F. Hamid, N. H. Lo, H. H. Ali Yeon, Mohd Shakaff, Prof. Dr. |
| author_sort |
Mamun, Ibne Reaz |
| title |
High degree of testability using full scan chain and ATPG-An industrial perspective |
| title_short |
High degree of testability using full scan chain and ATPG-An industrial perspective |
| title_full |
High degree of testability using full scan chain and ATPG-An industrial perspective |
| title_fullStr |
High degree of testability using full scan chain and ATPG-An industrial perspective |
| title_full_unstemmed |
High degree of testability using full scan chain and ATPG-An industrial perspective |
| title_sort |
high degree of testability using full scan chain and atpg-an industrial perspective |
| publisher |
Asian Network for Scientific Information |
| publishDate |
2010 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/9170 |
| _version_ |
1643789290974478336 |
| score |
13.214268 |