Description: High degree of testability using full scan chain and ATPG-An industrial perspective

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Bibliographic Details
Main Authors:	Mamun, Ibne Reaz, Lee, W. F., Hamid, N. H., Lo, H. H., Ali Yeon, Mohd Shakaff, Prof. Dr.
Format:	Article
Language:	English
Published:	Asian Network for Scientific Information 2010
Subjects:	Automatic test pattern generation Design for test DFT design methodology Guideline IC chip packaging Integrated circuit Scan chain Sharing pin for testing VLSI
Online Access:	http://dspace.unimap.edu.my/xmlui/handle/123456789/9170
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Summary:	Link to publisher's homepage at www.ansinet.com/