Floating point multiplication unit using FPGA
Access is limited to UniMAP community.
Saved in:
Main Author: | Woon Woei Zit |
---|---|
Other Authors: | Muhammad Imran Ahmad (Advisor) |
Format: | Learning Object |
Language: | English |
Published: |
Universiti Malaysia Perlis
2008
|
Subjects: | |
Online Access: | http://dspace.unimap.edu.my/xmlui/handle/123456789/3106 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Design and analysis of Floating Point multiplier
by: Zariah Asari
Published: (2008) -
Hardware implementation of RGB to HSL converter using FPGA
by: Soon, Voon Siew
Published: (2016) -
FPGA implementation on secure parking system
by: Mohd Khairul Akli Ab Ghani
Published: (2008) -
Design and implementation of real data fast fourier transform processor on field programmable gates array
by: Ahmed, Mohammed Kassim
Published: (2015) -
FPGA based Twofish Algorithm
by: Muhammad Imran, Ahmad, et al.
Published: (2009)