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Floating point multiplication unit using FPGA

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Bibliographic Details
Main Author: Woon Woei Zit
Other Authors: Muhammad Imran Ahmad (Advisor)
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis 2008
Subjects:
Field programmable gate arrays
Floating-point arithmetic
Semiconductors
Numerical calculations
Computer arithmetic
Multiplication
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/3106
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spelling my.unimap-31062008-11-12T03:07:49Z Floating point multiplication unit using FPGA Woon Woei Zit Muhammad Imran Ahmad (Advisor) Field programmable gate arrays Floating-point arithmetic Semiconductors Numerical calculations Computer arithmetic Multiplication Access is limited to UniMAP community. Field-programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combination functions such as decoders or simple mathematical functions. The architecture of floating point multiplication unit is designed using Cyclone FPGA chip. Floating point numbers are represented in IEEE 754 format which consists of 8 bits biased exponent, 23 bits fraction and sign bit. The suitability of FPGA as design platform is studied and performance of multiplication process is also observed for this project. Performance of multiplication process in various design aspects is done to achieve the objectives of this project. Design of architecture of floating point multiplication unit is done by using VHSIC hardware description language (VHDL) and Quartus II software using Altera UP3 Board which will be used as a simulation and synthesis tools. This project shows an example on how Floating Point Multiplication Unit Using FPGA is conducted using Quartus II software and VDHL. 2008-11-12T03:07:49Z 2008-11-12T03:07:49Z 2008-04 Learning Object http://hdl.handle.net/123456789/3106 en Universiti Malaysia Perlis School of Computer and Communication Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Field programmable gate arrays
Floating-point arithmetic
Semiconductors
Numerical calculations
Computer arithmetic
Multiplication
spellingShingle Field programmable gate arrays
Floating-point arithmetic
Semiconductors
Numerical calculations
Computer arithmetic
Multiplication
Woon Woei Zit
Floating point multiplication unit using FPGA
description Access is limited to UniMAP community.
author2 Muhammad Imran Ahmad (Advisor)
author_facet Muhammad Imran Ahmad (Advisor)
Woon Woei Zit
format Learning Object
author Woon Woei Zit
author_sort Woon Woei Zit
title Floating point multiplication unit using FPGA
title_short Floating point multiplication unit using FPGA
title_full Floating point multiplication unit using FPGA
title_fullStr Floating point multiplication unit using FPGA
title_full_unstemmed Floating point multiplication unit using FPGA
title_sort floating point multiplication unit using fpga
publisher Universiti Malaysia Perlis
publishDate 2008
url http://dspace.unimap.edu.my/xmlui/handle/123456789/3106
_version_ 1643787774636064768
score 13.214268

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