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An efficient modified booth multiplier architecture

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書誌詳細
主要な著者:	Razaidi, Hussin, Ali Yeon, Md Shakaff, Prof. Dr., Norina, Idris, Zaliman, Sauli, Prof. Dr., Rizalafande, Che Ismail, Afzan, Kamarudin
その他の著者:	shidee@unimap.edu.my
フォーマット:	Working Paper
言語:	English
出版事項:	Institute of Electrical and Electronics Engineers (IEEE) 2012
主題:	Booth multipliers Modified booth multipliers Multiplier architectures Architectural design Propagation delays multiplier architecture Sign extensions Transistor counts
オンライン･アクセス:	http://dspace.unimap.edu.my/xmlui/handle/123456789/19693
タグ:	タグ追加タグなし, このレコードへの初めてのタグを付けませんか!

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