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An efficient modified booth multiplier architecture

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Main Authors: Razaidi, Hussin, Ali Yeon, Md Shakaff, Prof. Dr., Norina, Idris, Zaliman, Sauli, Prof. Dr., Rizalafande, Che Ismail, Afzan, Kamarudin
Other Authors: shidee@unimap.edu.my
Format: Working Paper
Language:English
Published: Institute of Electrical and Electronics Engineers (IEEE) 2012
Subjects:
Booth multipliers
Modified booth multipliers
Multiplier architectures
Architectural design
Propagation delays
multiplier architecture
Sign extensions
Transistor counts
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/19693
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spelling my.unimap-196932012-06-05T05:07:01Z An efficient modified booth multiplier architecture Razaidi, Hussin Ali Yeon, Md Shakaff, Prof. Dr. Norina, Idris Zaliman, Sauli, Prof. Dr. Rizalafande, Che Ismail Afzan, Kamarudin shidee@unimap.edu.my Booth multipliers Modified booth multipliers Multiplier architectures Architectural design Propagation delays multiplier architecture Sign extensions Transistor counts Link to publisher's homepage at http://ieeexplore.ieee.org/ In this paper, we present the design of an efficient multiplication unit. This multiplier architecture is based on Radix 4 Booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's Modified Booth Encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the Simplified Sign Extension (SSE) method, the multiplication's output is incorrect. The 2nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the Carry signal. This modification has been made by rearranging the Boolean equation of the Carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% - 7% from other designers. 2012-06-05T05:07:01Z 2012-06-05T05:07:01Z 2008-12-01 Working Paper 978-142442315-6 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4786767 http://hdl.handle.net/123456789/19693 en Proceedings of the International Conference on Electronic Design (ICED) 2008 Institute of Electrical and Electronics Engineers (IEEE)
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Booth multipliers
Modified booth multipliers
Multiplier architectures
Architectural design
Propagation delays
multiplier architecture
Sign extensions
Transistor counts
spellingShingle Booth multipliers
Modified booth multipliers
Multiplier architectures
Architectural design
Propagation delays
multiplier architecture
Sign extensions
Transistor counts
Razaidi, Hussin
Ali Yeon, Md Shakaff, Prof. Dr.
Norina, Idris
Zaliman, Sauli, Prof. Dr.
Rizalafande, Che Ismail
Afzan, Kamarudin
An efficient modified booth multiplier architecture
description Link to publisher's homepage at http://ieeexplore.ieee.org/
author2 shidee@unimap.edu.my
author_facet shidee@unimap.edu.my
Razaidi, Hussin
Ali Yeon, Md Shakaff, Prof. Dr.
Norina, Idris
Zaliman, Sauli, Prof. Dr.
Rizalafande, Che Ismail
Afzan, Kamarudin
format Working Paper
author Razaidi, Hussin
Ali Yeon, Md Shakaff, Prof. Dr.
Norina, Idris
Zaliman, Sauli, Prof. Dr.
Rizalafande, Che Ismail
Afzan, Kamarudin
author_sort Razaidi, Hussin
title An efficient modified booth multiplier architecture
title_short An efficient modified booth multiplier architecture
title_full An efficient modified booth multiplier architecture
title_fullStr An efficient modified booth multiplier architecture
title_full_unstemmed An efficient modified booth multiplier architecture
title_sort efficient modified booth multiplier architecture
publisher Institute of Electrical and Electronics Engineers (IEEE)
publishDate 2012
url http://dspace.unimap.edu.my/xmlui/handle/123456789/19693
_version_ 1643792672111984640
score 13.222552

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