Coherent effect on LOCOS and STI technique for 0.18 µm CMOS technology using Taurus Workbench

• Main Author: Wan Shafie Wan Sulaiman
• Other Authors: Ruslinda A. Rahim (Advisor)
• Format: Learning Object
• Language: English
• Published: Universiti Malaysia Perlis 2008
• Subjects: Integrated circuits > Very large scale integration; Local oxidation of silicon (LOCOS); Shallow Trench Isolation (STI); Transistors; CMOS transistors; Metal oxide semiconductors, Complementary; Integrated circuits
• Online Access: http://dspace.unimap.edu.my/xmlui/handle/123456789/1955

LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) are two isolation techniques used in integrated circuit fabrication. Further device scaling using LOCOS technique is no longer practical for technology generations below 0.35 µm. STI technique was thus introduced because of its...