8-bits X 8-bits modified Booth 1’s complement multiplier

• 主要作者: Norafiza Salehan
• 其他作者: Norina Idris (Advisor)
• 格式: Learning Object
• 語言: English
• 出版: Universiti Malaysia Perlis 2008
• 主題: Altera Quartus II; Multipliers; Very Large Scale Integration (VLSI); Carry Save Adder (CSA); Multipliers (Mathematical analysis)
• 在線閱讀: http://dspace.unimap.edu.my/xmlui/handle/123456789/1934

With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed...