Uniformity improvement by integrated electrochemical-plating process for CMOS logic technologies

• 主要な著者: Wahab, Yasmin Abdul, Fadzil, Anuar, Soin, Norhayati, Fatmadiana, Sharifah, Chowdhury, Zaira Zaman, Hamizi, Nor Aliya, Pivehzhani, Omid Akbarzadeh, Sabapathy, Thennarasan, Al-Douri, Yarub
• フォーマット: 論文
• 出版事項: Elsevier 2019
• 主題: TK Electrical engineering. Electronics Nuclear engineering
• オンライン･アクセス: http://eprints.um.edu.my/24257/; https://doi.org/10.1016/j.jmapro.2019.01.025

Reliability of metal interconnects and the integration of inspection and metrology with process tools are advancing rapidly to overcome obstacles in down stream production. A significant drawback associated with metal interconnects which has resulted from the recent trend is the difficulty in obtaining uniform electroplated layer thicknesses across the maximum lateral dimension of the CMOS logic wafer. The prime objective of this paper is, to-root-cause uniformity troubleshooting by the adoption of integrated diffuser in electrochemical-plating (ECP) system optimizations. These are to quantify the best degree of uniformity and high resistivity to enhance an even current distribution on the wafer. The results show that uniformity of the deposited film has been improved significantly with 1.9%. i.e., maximum deviation of the deposited film thickness is at about 1.9% of the average film thickness, while standard electroplating processes typically achieves uniformity at best within 5.5%. Furthermore, the origin of “hot spots’’ that caused poor uniformity was identified and greatly overcome with the improved ECP system comprising an integrated diffuser design and process modifications in real troubleshooting of back –end operation line (BEOL) of semiconductor foundry. © 2019 The Society of Manufacturing Engineers