Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi

This paper present an analysis and design of Sample and Hold (SH) circuit for front end block pipelined ADC using 0.18um CMOS technology. The objective of this project is to design a sample and hold circuit and analyzing in term of low power and high speed with two different topologies, which are tw...

Full description

Saved in:
Bibliographic Details
Main Author: Mohd Tarmizi, Suhaib
Format: Thesis
Language:English
Published: 2013
Subjects:
Online Access:https://ir.uitm.edu.my/id/eprint/98392/1/98392.PDF
https://ir.uitm.edu.my/id/eprint/98392/
Tags: Add Tag
No Tags, Be the first to tag this record!