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Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi

This paper present an analysis and design of Sample and Hold (SH) circuit for front end block pipelined ADC using 0.18um CMOS technology. The objective of this project is to design a sample and hold circuit and analyzing in term of low power and high speed with two different topologies, which are tw...

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Main Author: Mohd Tarmizi, Suhaib
Format: Thesis
Language:English
Published: 2013
Subjects:
T Technology (General)
Online Access:https://ir.uitm.edu.my/id/eprint/98392/1/98392.PDF
https://ir.uitm.edu.my/id/eprint/98392/
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spelling my.uitm.ir.983922024-08-06T09:42:25Z https://ir.uitm.edu.my/id/eprint/98392/ Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi Mohd Tarmizi, Suhaib T Technology (General) This paper present an analysis and design of Sample and Hold (SH) circuit for front end block pipelined ADC using 0.18um CMOS technology. The objective of this project is to design a sample and hold circuit and analyzing in term of low power and high speed with two different topologies, which are two stage operational amplifier and folded cascode operational amplifier. The analysis of op amp parameters is done for 0.18um CMOS technology. SILVACO EDA tools have been used for schematic design and simulation. Complete Sample and Hold circuit has been designed with 1.8V Vpp, 1.8V voltage supply and 5Mz sampling frequency. The power consumption for two stage operational amplifiers is 0.08 lmW and for folded cascode operational amplifier is 0.593mW. The propagation delay of the circuit is 131.15ns for two stage operational amplifier and 2.7402ns for folded cascode operational amplifier. Based on the analysis and design, two stage operational amplifier can give low power consumption and low speed while folded cascode operational amplifier can give high power consumption but high speed. 2013 Thesis NonPeerReviewed text en https://ir.uitm.edu.my/id/eprint/98392/1/98392.PDF Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi. (2013) Degree thesis, thesis, Universiti Teknologi MARA (UiTM).
institution Universiti Teknologi Mara
building Tun Abdul Razak Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Mara
content_source UiTM Institutional Repository
url_provider http://ir.uitm.edu.my/
language English
topic T Technology (General)
spellingShingle T Technology (General)
Mohd Tarmizi, Suhaib
Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
description This paper present an analysis and design of Sample and Hold (SH) circuit for front end block pipelined ADC using 0.18um CMOS technology. The objective of this project is to design a sample and hold circuit and analyzing in term of low power and high speed with two different topologies, which are two stage operational amplifier and folded cascode operational amplifier. The analysis of op amp parameters is done for 0.18um CMOS technology. SILVACO EDA tools have been used for schematic design and simulation. Complete Sample and Hold circuit has been designed with 1.8V Vpp, 1.8V voltage supply and 5Mz sampling frequency. The power consumption for two stage operational amplifiers is 0.08 lmW and for folded cascode operational amplifier is 0.593mW. The propagation delay of the circuit is 131.15ns for two stage operational amplifier and 2.7402ns for folded cascode operational amplifier. Based on the analysis and design, two stage operational amplifier can give low power consumption and low speed while folded cascode operational amplifier can give high power consumption but high speed.
format Thesis
author Mohd Tarmizi, Suhaib
author_facet Mohd Tarmizi, Suhaib
author_sort Mohd Tarmizi, Suhaib
title Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
title_short Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
title_full Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
title_fullStr Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
title_full_unstemmed Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi
title_sort analysis and design of a low power, high speed sample and hold circuit for pipelined adc using 0.18um cmos technology / suhaib mohd tarmizi
publishDate 2013
url https://ir.uitm.edu.my/id/eprint/98392/1/98392.PDF
https://ir.uitm.edu.my/id/eprint/98392/
_version_ 1806692693777055744
score 13.211869

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