Simulation of planar and FINFET transistor model for digital gate applications: article / Siti Aishah Abu Salim
Abstract -In this work, FinFET (dual-gate)r transistor is simulated using computer added design (CAD) tools to replacethe conventional planar MOSFET. Now a day planar transistors are no longer clean due to current leakage during one-off switches. Thus, these effects have caused some head and power...
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| Format: | Article |
| Language: | English |
| Published: |
2013
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| Online Access: | https://ir.uitm.edu.my/id/eprint/105274/1/105274.pdf https://ir.uitm.edu.my/id/eprint/105274/ |
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| Summary: | Abstract -In this work, FinFET (dual-gate)r transistor is simulated using computer added design (CAD) tools to replacethe conventional planar MOSFET. Now a day planar transistors are no longer clean due to current leakage during one-off switches. Thus, these effects have caused some head and power issues. FinFET transistors offer superior performance as the device is scaled into the nanometer. Therefore, the ON current was investigated by analysing the I-V characteristic. Also the gate sizing was investigated and the results have shown the differences in their performances. In addition, the SPICE models of 32 nm were employed for inverter, NAND and NOR gates and the results were verified by DC and AC analysis. The results indicate that FinFET circuits have better performance and produced less leakage when compared to planar MOSFET. |
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