FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard

• Main Authors: Shyamsi, M., Ibrahimy, Muhammad Ibn, Motakabber, S. M. A., Ahsan, M. R.
• Format: Article
• Language: English
• Published: Journal of Communications Technology, Electronics and Computer Science 2015
• Subjects: T Technology (General)
• Online Access: http://irep.iium.edu.my/45503/1/2-50-1-PB.pdf; http://irep.iium.edu.my/45503/; http://jctecs.com/index.php/com/index

This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis, etc. Implementation of floating-point multiplication is handy and easy for high level language. However, it is a challenging task to implement a floating-point multiplication in hardware level or in low level language due to the complexity of algorithms. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.