VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY

This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design.

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Main Author: A/L Arulnathan, Jonathan
Format: Final Year Project
Language:English
Published: Universiti Teknologi PETRONAS 2018
Subjects:
Online Access:http://utpedia.utp.edu.my/18949/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf
http://utpedia.utp.edu.my/18949/
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spelling my-utp-utpedia.189492019-03-18T11:41:50Z http://utpedia.utp.edu.my/18949/ VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY A/L Arulnathan, Jonathan TK Electrical engineering. Electronics Nuclear engineering This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design. Universiti Teknologi PETRONAS 2018-09 Final Year Project NonPeerReviewed application/pdf en http://utpedia.utp.edu.my/18949/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf A/L Arulnathan, Jonathan (2018) VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY. Universiti Teknologi PETRONAS.
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
A/L Arulnathan, Jonathan
VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
description This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design.
format Final Year Project
author A/L Arulnathan, Jonathan
author_facet A/L Arulnathan, Jonathan
author_sort A/L Arulnathan, Jonathan
title VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_short VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_full VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_fullStr VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_full_unstemmed VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY
title_sort vco development using 130nm cmos technology
publisher Universiti Teknologi PETRONAS
publishDate 2018
url http://utpedia.utp.edu.my/18949/1/22379%20Jonathan%20Arulnathan%20FYP%20Final%20Report.pdf
http://utpedia.utp.edu.my/18949/
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score 13.188404