Design of an ADC controller for 5-stage pipeline RISC32 microprocessor.

• Main Author: Tan, Yan kai
• Format: Final Year Project / Dissertation / Thesis
• Published: 2022
• Subjects: TA Engineering (General). Civil engineering (General); TE Highway engineering. Roads and pavements; TG Bridge engineering; TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utar.edu.my/4633/1/fyp_CT_2022_TYK.pdf; http://eprints.utar.edu.my/4633/

This project is about the Analog-to-Digital Converter (ADC) controller unit design and implementation for academic purpose. Throughout the project, XADC from Xilinx is used for simulation purpose. The development of this project will begin with the design of the ADC controller unit. The datasheet of the XADC which is provided by the Xilinx is studied in the beginning of design process in order to match all the requirements and protocols to ensure the functionality of ADC controller unit. The RTL design flow will be used throughout the project development and the micro-architectural level design will be focused more as the ADC controller to be designed is in the unit level. The ADC controller unit and the internal block will be modelled by using Verilog HDL. The XADC with a model name of ug480 is obtained from the IP Catalog of Vivado and it will be instantiated in RISC32. The ug480 module also comes with a constraint and a simple dataset that are needed for simulation purpose. The specifications of the ADC controller unit and the instantiation of ug480 will be functionally verified by writing testbenches in Verilog HDL. Besides, the specific registers that needed for the communication between XADC and ADC controller unit will also be tested for functionality. Some of the functions provided by ug480 are not implemented as they are irrelevant to the learning course. After the ADC controller unit has been functionally verified, it will be integrated into the existing 5-stage pipeline RISC32 processor which is developed in UTAR. This involves the interfacing between the ADC controller and the RISC32 based on the I/O memory mapping technique. Moreover, a simple Interrupt Service Routine will be specifically developed and implemented on the RISC32 to perform certain instructions whenever there is an interrupt signal sent by XADC.Lastly, a simple assembly program code will be specifically designed to test the overall functionality. Other than basic function in the ADC controller unit, multiple interrupt and multiple trap case will also be tested since ADC controller unit is one of the IO devices and it will eventually work with other IO devices at the same time after the integration is completed.