Clock domain crossing design for 5-Stage Pipeline RISC32

• Main Author: Leong, Kar Yong
• Format: Final Year Project / Dissertation / Thesis
• Published: 2022
• Subjects: TA Engineering (General). Civil engineering (General); TF Railroad engineering and operation; TG Bridge engineering; TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utar.edu.my/4627/1/fyp_CT__2022_LKY.pdf; http://eprints.utar.edu.my/4627/

This project is about the clock domain crossing (CDC) circuit design and implementation in RISC32 for academic purposes. Due to the I/O system usually requires a lower frequency to operate as compared to the CPU clock, the CDC circuit being implemented in RISC32 can allow its I/O system to work in d...