Optimization of an Integrated Circuit Device by Improving ITS VLSI Design from RTL to GDSII

• Main Author: Thee, Kang Wei
• Format: Final Year Project / Dissertation / Thesis
• Published: 2016
• Subjects: TJ Mechanical engineering and machinery
• Online Access: http://eprints.utar.edu.my/2304/1/BEE%2D2016%2D1200074%2D1.pdf; http://eprints.utar.edu.my/2304/

VLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. In this project, the front-end design and back-end design were done in order to improve and optimize an 8051 microcontroller-based core. Logic synthesis, physical design, physical verification and others are done by using EDA tools, namely Synopsys Design Compiler and Synopsys IC Compiler. EDA tools provide the design automations for IC design process which can reduce the design TAT. In order to reduce the design cost, the chip-area is reduced as small as possible. The performance of the chip is improved by 10 times of its original clock frequency. Most of the violations that exist in the design are fixed. The optimized gate-level netlist is generated by Design Compiler in ddc format. The final layout is generated by IC Compiler. The layout and netlist have passed the verifications like static timing analysis and others. Lastly, the GDSII file is streamed out from IC Compiler.