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Implementing digital finite impulse response filter using FPGA

This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked...

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Main Authors: Razak, Abdul Hadi Abdul, Zaharin, Muhamad Iqbal Abu, Haron, Nor Zaidi
Format: Conference or Workshop Item
Language:English
Published: 2007
Subjects:
QA76 Computer software
Online Access:http://repo.uum.edu.my/4561/1/Im.pdf
http://repo.uum.edu.my/4561/
http://dx.doi.org/10.1109/APACE.2007.4603854
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spelling my.uum.repo.45612013-05-27T04:19:44Z http://repo.uum.edu.my/4561/ Implementing digital finite impulse response filter using FPGA Razak, Abdul Hadi Abdul Zaharin, Muhamad Iqbal Abu Haron, Nor Zaidi QA76 Computer software This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop.All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM.The program is written in VHDL source code based on application Xilinx notes [1] that describe the design of an FIR filter.The software tools have been used are Xilinx ISE Webpack 8.1, ModelSim 6.1e and Matlab 7.0. 2007-12-04 Conference or Workshop Item PeerReviewed application/pdf en http://repo.uum.edu.my/4561/1/Im.pdf Razak, Abdul Hadi Abdul and Zaharin, Muhamad Iqbal Abu and Haron, Nor Zaidi (2007) Implementing digital finite impulse response filter using FPGA. In: Asia-Pacific Conference on Applied Electromagnetics, 2007 (APACE 2007), 4-6 Dec. 2007 , Kuala Lumpur. http://dx.doi.org/10.1109/APACE.2007.4603854 doi:10.1109/APACE.2007.4603854
institution Universiti Utara Malaysia
building UUM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Utara Malaysia
content_source UUM Institutionali Repository
url_provider http://repo.uum.edu.my/
language English
topic QA76 Computer software
spellingShingle QA76 Computer software
Razak, Abdul Hadi Abdul
Zaharin, Muhamad Iqbal Abu
Haron, Nor Zaidi
Implementing digital finite impulse response filter using FPGA
description This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop.All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM.The program is written in VHDL source code based on application Xilinx notes [1] that describe the design of an FIR filter.The software tools have been used are Xilinx ISE Webpack 8.1, ModelSim 6.1e and Matlab 7.0.
format Conference or Workshop Item
author Razak, Abdul Hadi Abdul
Zaharin, Muhamad Iqbal Abu
Haron, Nor Zaidi
author_facet Razak, Abdul Hadi Abdul
Zaharin, Muhamad Iqbal Abu
Haron, Nor Zaidi
author_sort Razak, Abdul Hadi Abdul
title Implementing digital finite impulse response filter using FPGA
title_short Implementing digital finite impulse response filter using FPGA
title_full Implementing digital finite impulse response filter using FPGA
title_fullStr Implementing digital finite impulse response filter using FPGA
title_full_unstemmed Implementing digital finite impulse response filter using FPGA
title_sort implementing digital finite impulse response filter using fpga
publishDate 2007
url http://repo.uum.edu.my/4561/1/Im.pdf
http://repo.uum.edu.my/4561/
http://dx.doi.org/10.1109/APACE.2007.4603854
_version_ 1644278780200484864
score 13.251813

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