Implementing digital finite impulse response filter using FPGA
This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked...
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| 主要な著者: | , , |
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| フォーマット: | Conference or Workshop Item |
| 言語: | English |
| 出版事項: |
2007
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| 主題: | |
| オンライン･アクセス: | http://repo.uum.edu.my/4561/1/Im.pdf http://repo.uum.edu.my/4561/ http://dx.doi.org/10.1109/APACE.2007.4603854 |
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| 要約: | This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop.All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM.The program is written in VHDL source code based on application Xilinx notes [1] that describe the design of an FIR filter.The software tools have been used are Xilinx ISE Webpack 8.1, ModelSim 6.1e and Matlab 7.0.
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