Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing

• Main Authors: Mohd Fazil, Azlan Faizal, Mohd Shaharanee, Izwan Nizal, Mohd Jamil, Jastini, Ang, Jin Sheng
• Format: Article
• Language: English
• Published: kansai university, japan 2020
• Subjects: QA75 Electronic computers. Computer science
• Online Access: http://repo.uum.edu.my/28159/1/TRKU%2062%2017%202020%203625%203630.pdf; http://repo.uum.edu.my/28159/; https://www.kansaiuniversityreports.com/search-article

Semiconductor including integrated circuit (IC) is an expensive and complicated process. The trend of semiconductor packaging is going towards better performance with lower power consumption packages. Thus, the single-die packaging trend has evolved into multi-die packaging. The evolution of multi-die packaging requires more tools and processing steps in the assembly process. Furthermore, any die is tested at Class, and detected faulty will cause the whole package to be scrapped. These factors cause a bigger loss in production yield to compare to the single-die packaging. A new framework is suggested for model training and evaluation for the application of machine learning in the semiconductor test. The proposed new framework will be able to provide a range of possible recall rates from minimum to maximum to identify which machine learning algorithms specifically.