Optimized encoder architecture for structured low density parity check codes of short length

• Main Authors: Anggraeni, S., Hussin, F.A., Jeoti, V.
• Format: Conference or Workshop Item
• Published: IEEE Computer Society 2014
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906346399&doi=10.1109%2fICIAS.2014.6869526&partnerID=40&md5=e3e8069bf911ea67a8f1c29638509541; http://eprints.utp.edu.my/32118/

This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The propose...