Threading optimization of the AEMB microprocessor

• Main Authors: Mohamed, M., Sebastian, P., Hiung, L.H., Ngiap, S.T.S.
• Format: Conference or Workshop Item
• Published: Institute of Electrical and Electronics Engineers Inc. 2014
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84946686657&doi=10.1109%2fICCSCE.2014.7072785&partnerID=40&md5=7097e0ca4ddb80a25ee68922d96b4e35; http://eprints.utp.edu.my/31306/

This paper aims at explaining the architecture of the AEMB and optimizing its threading model. AEMB is a soft core, open source processor designed for FPGA implementation. AEMB uses a fine grained model that interleaves threads one instruction at a time with separate register sets for each thread. The chosen optimization is to change the current threading model to a Coarse-grained that switches threads on branch instructions. The advantage of this approach is that control hazards will be avoided in most cases hence stalling the pipeline till branch targets are calculated will be drastically decreased. This is quite an improvement over the previous core where the processor stalls for one cycle on any branch instruction encountered. The disadvantage to the coarse grained threading model is that data hazards that can't be forwarded can now cause the processor to stall up to three cycles in the worst case scenario compared to only one stall in the old model. As for Area consumption on FPGA, synthesis showed that the modified core utilizes double the number of LUTs that the original AEMB needs but there was no significant increase in the number of register. Further quantitative analysis is necessary to determine the total gain in performance by running the suitable benchmarks on both versions of the processor. © 2014 IEEE.