Configurable 2 bits per cycle successive approximation register for analog to digital converter on FPGA

• Main Authors: Hooi, L.Y., Hiung, L.H., Drieberg, M., Sebastian, P.
• Format: Article
• Published: Institute of Electrical and Electronics Engineers Inc. 2017
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85011966285&doi=10.1109%2fICIAS.2016.7824120&partnerID=40&md5=3d7fc83d8e7ec9364c4374cdbdd4b73d; http://eprints.utp.edu.my/20189/

Analog-to-Digital Converter (ADC) technology has been advancing to achieve a balance between speeds, size and cost. Successive approximation register (SAR) ADC is very popular for medium-to-high resolution as it is small but has difficulties in achieving high speed while flash ADC is big and not cost effective. Also, for different purposes, ADC have different resolution requirement. Producing ADCs with different resolution increases cost if it is not used in large scale production. In this paper, we propose to solve the issues of speed, size and cost by presenting a configurable 2 bits per cycle successive approximation register (SAR) ADC for FPGA implementation based on modification from successive approximation method. This SAR utilizes three comparators, instead of one comparator in normal SAR ADC. This enables the SAR to convert 2 bits at a time hence, reducing the conversion time by half, while at the same time, the resolution of this presented SAR is configurable. This increases the reusability of this SAR ADC for various different requirements of resolution. The design is implemented on Altera DE2 board with Cyclone II FPGA at a clock rate of 50MHz and can be boosted to 136MHz. On average, N cycles is needed for 2N bit resolution. © 2016 IEEE.