High rate (3, k) regular LDPC encoder architecture
This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC e...
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my.utp.eprints.119942017-01-19T08:23:07Z High rate (3, k) regular LDPC encoder architecture Anggraeni, Silvia Hussin, Fawnizu Azmadi Jeoti , Varun This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R ≥ 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R ≥ 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H). 2011 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/11994/1/06136390.pdf Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Jeoti , Varun (2011) High rate (3, k) regular LDPC encoder architecture. In: 3rd National Postgraduate Conference, 19-20 September 2011, Universiti Teknologi PETRONAS, Perak, Malaysia. http://eprints.utp.edu.my/11994/ |
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This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R ≥ 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R ≥ 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H). |
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Conference or Workshop Item |
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Anggraeni, Silvia Hussin, Fawnizu Azmadi Jeoti , Varun |
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Anggraeni, Silvia Hussin, Fawnizu Azmadi Jeoti , Varun High rate (3, k) regular LDPC encoder architecture |
author_facet |
Anggraeni, Silvia Hussin, Fawnizu Azmadi Jeoti , Varun |
author_sort |
Anggraeni, Silvia |
title |
High rate (3, k) regular LDPC encoder architecture |
title_short |
High rate (3, k) regular LDPC encoder architecture |
title_full |
High rate (3, k) regular LDPC encoder architecture |
title_fullStr |
High rate (3, k) regular LDPC encoder architecture |
title_full_unstemmed |
High rate (3, k) regular LDPC encoder architecture |
title_sort |
high rate (3, k) regular ldpc encoder architecture |
publishDate |
2011 |
url |
http://eprints.utp.edu.my/11994/1/06136390.pdf http://eprints.utp.edu.my/11994/ |
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1738655998609981440 |
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13.18916 |