High Throughput Architecture for Low Density Parity Check (LDPC) Encoder
This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed archit...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2013
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| Online Access: | http://eprints.utp.edu.my/11981/1/ArchEncLDPC.pdf http://eprints.utp.edu.my/11981/ |
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| Summary: | This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. |
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