A streaming multi-class support vector machine classification architecture for embedded systems

• Main Authors: Sirkunan, J., Tang, J. W., Shaikh Husin, N., Marsono, M. N.
• Format: Article
• Language: English
• Published: Institute of Advanced Engineering and Science 2019
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/89921/1/JeevanSirkunan2019_AStreamingMultiClassSupportVector.pdf; http://eprints.utm.my/id/eprint/89921/; https://dx.doi.org/10.11591/ijeecs.v16.i3.pp1286-1296

Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated Support Vector Machine (SVM). Computational complexity of SVM classification makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, testing data are mostly stored on external memory. Data are transferred in streams with the maximum bandwidth limited to the bus bandwidth. The hardware implementation for SVM classification needs to be sufficiently fast to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in the streaming architecture. In this work, we propose a streaming-architecture multi-class SVM classification for an embedded system that is fully pipelined and able to process data continuously without any need to throttle data stream input. The proposed design is targeted for embedded platform where testing data is transferred in streams from external memories. The architecture is modeled using Verilog and the evaluation is targeted for Altera Cyclone IV field programmable gate array platform. Performance profiling on the proposed architecture is done with regard to the number of features and support vectors. For validation, the proposed architecture is simulated using ModelSim and the results are compared with LibSVM. Based on the simulation result, the proposed architecture is able to produce a throughput of 1/Nf classification per clock cycle, where Nf is the number of features.