Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter
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my.utm.837732019-09-30T13:49:07Z http://eprints.utm.my/id/eprint/83773/ Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa 2018 Article NonPeerReviewed Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa (2018) Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter. PROCEEDINGS OF 2018 ELECTRICAL ENGINEERING SYMPOSIUM (EES2018) . |
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Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa |
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Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
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Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa |
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Izam Kamisian, Syed Ahmad Asyraf Syed Mustafa |
title |
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
title_short |
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
title_full |
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
title_fullStr |
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
title_full_unstemmed |
Using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
title_sort |
using altera de1-soc: integrating hard processor system (hps) and field programmable gate array (fpga) cores for median filter |
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2018 |
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http://eprints.utm.my/id/eprint/83773/ |
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13.18916 |