Ping-lock round robin arbiter

• Main Authors: Monemi, A., Ooi, C. Y., Palesi, M., Marsono, M. N.
• 格式: Article
• 出版: Elsevier Ltd 2017
• 主題: TK Electrical engineering. Electronics Nuclear engineering
• 在線閱讀: http://eprints.utm.my/id/eprint/76961/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85016468889&doi=10.1016%2fj.mejo.2017.03.004&partnerID=40&md5=1ea56215940807f2c124ef28323c5d6d

Arbiter is the core element in shared-resources systems such as in network-on-chip (NoC), conventional interconnection buses and computer network switch schedulers. Arbiters are located in the critical path delay (CPD) of these systems, that necessitates fast and fair arbitration. This paper proposes two gate-level arbiter architectures. The first arbiter is an improved ping-pong arbiter (IPPA) that is optimized to offer lower execution delay compared to existing round robin arbiters (RRAs). One of the main disadvantages of ping-pong arbiter (PPA) is that fair arbitration is limited to the uniformly-distributed active requests pattern. To solve this problem, we propose a new gate-level RRA, called ping-lock arbiter (PLA). PLA, which is an improved IPPA offers fair arbitration under any distribution of active requests and has the advantage of low execution delay. The FPGA and ASIC implementations of PLA show up to 18% and 12% improvement in average delay, respectively, when compared to existing RRAs in literature.