The implementation of a pipelined floating-point CORDIC coprocessor on NIOS II soft processor

This paper discusses the implementation of a pipelined floating-point Coordinate Rotation Digital Computer (CORDIC) coprocessor using Field Programmable Gate Array (FPGA) to accelerate the computation speed in solving elementary functions on NIOS II soft processor. Examples of the elementary functio...

Full description

Saved in:
Bibliographic Details
Main Authors: Ibrahim, Muhammad Nasir, Chen, Kean Tack, Idroas, Mariani, Yahya, Zuraimi
Format: Conference or Workshop Item
Published: 2015
Subjects:
Online Access:http://eprints.utm.my/id/eprint/60606/
http://www.iraj.in/journal/journal_file/journal_pdf/1-124-142900609715-20.pdf
Tags: Add Tag
No Tags, Be the first to tag this record!
Be the first to leave a comment!
You must be logged in first