An empirical evaluation of topologies for large scale NoC

• Main Authors: Baboli, Mehdi, Shaikh Husin, Nasir
• Format: Article
• Published: Institute of Advanced Engineering and Science 2014
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/59607/; http://ijeecs.iaescore.com/index.php/IJEECS/article/view/3929

In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation to increase the performance quality of the existing network-on-chip (NoC). Diminishing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a popular NoC topology, i.e., mesh, and evaluated it in terms of latency, maximum delay, average throughput, and total energy under different routing algorithms, number of router buffers, and random traffic model. We selected two sizes of NoC, 12×12 and 16×16, to represent large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrate that when the network size is large and number of buffers is insufficient, popular routing algorithms cannot ensure good network performance and almost all routing algorithms have the same performance for the large scale NoCs.