An empirical evaluation of topologies for large scale NoC

In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation to increase the performance quality of the existing network-on-chip (NoC). Diminishing...

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Main Authors: Baboli, Mehdi, Shaikh Husin, Nasir
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出版: Institute of Advanced Engineering and Science 2014
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在線閱讀:http://eprints.utm.my/id/eprint/59607/
http://ijeecs.iaescore.com/index.php/IJEECS/article/view/3929
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spelling my.utm.596072022-04-26T02:49:35Z http://eprints.utm.my/id/eprint/59607/ An empirical evaluation of topologies for large scale NoC Baboli, Mehdi Shaikh Husin, Nasir TK Electrical engineering. Electronics Nuclear engineering In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation to increase the performance quality of the existing network-on-chip (NoC). Diminishing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a popular NoC topology, i.e., mesh, and evaluated it in terms of latency, maximum delay, average throughput, and total energy under different routing algorithms, number of router buffers, and random traffic model. We selected two sizes of NoC, 12×12 and 16×16, to represent large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrate that when the network size is large and number of buffers is insufficient, popular routing algorithms cannot ensure good network performance and almost all routing algorithms have the same performance for the large scale NoCs. Institute of Advanced Engineering and Science 2014-12 Article PeerReviewed Baboli, Mehdi and Shaikh Husin, Nasir (2014) An empirical evaluation of topologies for large scale NoC. TELKOMNIKA Indonesian Journal of Electrical Engineering, 12 (12). pp. 8133-8140. ISSN 2302-4046 http://ijeecs.iaescore.com/index.php/IJEECS/article/view/3929
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Baboli, Mehdi
Shaikh Husin, Nasir
An empirical evaluation of topologies for large scale NoC
description In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation to increase the performance quality of the existing network-on-chip (NoC). Diminishing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a popular NoC topology, i.e., mesh, and evaluated it in terms of latency, maximum delay, average throughput, and total energy under different routing algorithms, number of router buffers, and random traffic model. We selected two sizes of NoC, 12×12 and 16×16, to represent large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrate that when the network size is large and number of buffers is insufficient, popular routing algorithms cannot ensure good network performance and almost all routing algorithms have the same performance for the large scale NoCs.
format Article
author Baboli, Mehdi
Shaikh Husin, Nasir
author_facet Baboli, Mehdi
Shaikh Husin, Nasir
author_sort Baboli, Mehdi
title An empirical evaluation of topologies for large scale NoC
title_short An empirical evaluation of topologies for large scale NoC
title_full An empirical evaluation of topologies for large scale NoC
title_fullStr An empirical evaluation of topologies for large scale NoC
title_full_unstemmed An empirical evaluation of topologies for large scale NoC
title_sort empirical evaluation of topologies for large scale noc
publisher Institute of Advanced Engineering and Science
publishDate 2014
url http://eprints.utm.my/id/eprint/59607/
http://ijeecs.iaescore.com/index.php/IJEECS/article/view/3929
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score 13.250246