An empirical evaluation of topologies for large scale NoC
In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation to increase the performance quality of the existing network-on-chip (NoC). Diminishing...
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Format: | Article |
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Institute of Advanced Engineering and Science
2014
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Online Access: | http://eprints.utm.my/id/eprint/59607/ http://ijeecs.iaescore.com/index.php/IJEECS/article/view/3929 |
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