Cover Image

VHDL modelling and asic design of a shortest-path processor core for network routing

Saved in:

Bibliographic Details
Main Author:	Teoh, Giap Seng
Format:	Thesis
Published:	2003
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/42788/ http://libraryopac.utm.my/client/en_AU/main/search/detailnonmodal/ent:$002f$002fSD_ILS$002f0$002fSD_ILS:360530/one?qu=VHDL+modelling+and+asic+design+of+a+shortest-path+processor+core+for+network+routing
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

VHDL design of A 32-Bit RISC processor core for FPGA implementation
by: Marsono, Muhammad Nadzir
Published: (2001)

High-Speed shortest path co-processor design
by: Idris, Mohd Yamani Idna, et al.
Published: (2009)

Scheduling of routing table calculation schemes in open shortest path first using artificial neural network
by: Abu Yazid, Mohamad Haider
Published: (2013)

ASIC design flow
by: Dass, Sreedharan Baskara, et al.
Published: (2011)

Routing problem in rectangular mesh network using shortest path based Greedy method
by: Noraziah, Adzhar, et al.
Published: (2019)

Determination of the shortest path by using genetic algorithms
by: Abu Hassan, Mohd. Fadzil
Published: (2008)

Asic design of a kohonen neural network microchip
by: Rajah, Avinash, et al.
Published: (2004)

Asic design for healthiness recognition of agriculture
by: Chin, Linn Kern
Published: (2020)

Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing
by: Ch'ng, Heng Sun
Published: (2007)

A hybrid algorithm for finding shortest path in network routing.
by: Soltan Aghaei, Mohammad Reza, et al.
Published: (2009)

INPUT/OUTPUT PROCESSOR IP CORE- ASHl
by: HASHIM, ABDULLAH SHAMIL
Published: (2011)

RTL design of SHA-512 processor core for secure message hashing
by: Chua, Lee Ping
Published: (2008)

Verilog design of bist on AES256 processor core with FPGA implementation
by: Hew, Kean Yung
Published: (2008)

Traffic Balancing Method in Shortest Path Routing
by: Mohamed Abdulqader, Makarem
Published: (2007)

Shortest Path Routing Using Heuristic Search
by: Alaiwan, Ahmed Omran A.
Published: (2006)

A comparison of load-distributive path routing and shortest path routing in wireless ad hoc networks
by: Habib, I., et al.
Published: (2014)

Implementation of a soft core processor on a FPGA
by: Woo, Chi Liang
Published: (2011)

Multi-core 16-bit CPUs for PLC processor
by: Gan, Chi Qian
Published: (2022)

DSP asic module design for natural frequency of ECG signal
by: Abdul Kadir, Nurul Ashikin, et al.
Published: (2015)

Design and analysis multiple paths trace back and reconstruction module for DNA sequence alignment accelerator using ASIC design flow / Nurul Ain Husaini
by: Husaini, Nurul Ain
Published: (2010)

An FPGA implementation of RSA processor core for public-key cryptosystem
by: Tan, Siang Lin
Published: (2001)

Obstacle Avoidance for Vision-Based Automated Guided Vechicle (AGV) Using Shortest path Planning
by: Mohd Shah, Hairol Nizam, et al.
Published: (2008)

Verilog design of a 256-bit AES crypto processor core
by: Lai, Yit Pin
Published: (2007)

Design of a high speed and low latency crypto-processor ASIC
by: Ali, Md. Liakot, et al.
Published: (2008)

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
by: Ismail, Mohd. Izuan
Published: (2006)

Register transfer level design of compression processor core using verilog hardware description language
by: Mohd. Sabri, Roslee
Published: (2007)

USB soft core with altera Nios processor
by: Cheah, Chee Teong
Published: (2007)

Electrocardiogram QRS detection hardware accelerator for ASIC implementation
by: Lim, Zhi Qing
Published: (2020)

Asic implementation of low latency montgomery modular exponentiation
by: Liew, Pui Yen
Published: (2022)

Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
by: Abdul Rahman, Abdul Aziz
Published: (2003)

Advancing system integration: verilog-based hardware implementation of an asic interface for three amba processors
by: Motakabber, S. M. A., et al.
Published: (2024)

Modelling dynamic routing for 3D shortest path analysis
by: Musliman, Ivin Amri, et al.
Published: (2008)

A Matrix Usage for Load Balancing in Shortest Path Routing
by: Mustafa, Nor Musliza
Published: (2009)

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)
by: Liew, Meng Wei
Published: (2008)

Implementation of k-shortest paths computation on a molecular computer via hybridization-ligation and parallel overlap assembly
by: Ibrahim, Zuwairie, et al.
Published: (2006)

Routing problem in rectangular mesh network using shortest path based Greedy method
by: Noraziah, Adzhar, et al.
Published: (2019)

Hopfield model for shortest path computation and routing in ATM network / by Lee Chee Weng
by: Lee, Chee Weng
Published: (2001)

Identification of least congested and shortest distance path in traffic network
by: Ting, Kien Hua, et al.
Published: (2018)

ASIC implementation and optimization of 16 bit SDRAM memory controller
by: Alias, Nurul Ezaila, et al.
Published: (2020)

Design of a route lookup processor for implementation in a FPGA-based system-on chip (SoC)
by: Teh , J-Wing
Published: (2004)